This invention relates generally to delay circuits and specifically to a control circuit for delay elements comprising CMOS (Complementary Metal Oxide Semiconductor) and BICMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated circuit devices. As is well known, similar devices on a common integrated circuit chip exhibits a very high degree of correlation to each other, whereas similar devices on different chips exhibit very poor correlation. For example, it is not uncommon for transistors or other devices on the same IC chip to vary in operating characteristics by less than 1%, whereas similar devices on different chips may vary by 20% or more.
The elements and circuits in the preferred embodiment of the invention utilize BICMOS devices, such as transmission gates and inverters. The current switching ability of these devices is a direct function of applied gate voltage. Within operating limits, the higher the applied gate voltage, the larger the current flow in the device. The invention generally provides a novel and superior delay circuit for integrated circuit use that is especially suitable for high frequency applications where the delays are in the range of a few nanoseconds. The present invention is specifically directed to a delay circuit having a phase locked loop (PLL) voltage controlled delay element. The invention claimed in copending application Ser. No. 613,178 is directed to the voltage controlled delay element and the inventions in applications Ser. Nos. 613,175 and 614,189 are directed to a frequency multiplier circuit and to a pulse width measuring circuit, respectively, that use voltage controlled delay elements.